Fully Integrated CMOS Frequency Synthesizer for ZigBee Applications

Authors:
Saurabh Kumar Singh;T. K. Bhattacharyya;Ashudeb Dutta
Affiliations:
Indian Institute of Technology-Kharagpur;Indian Institute of Technology-Kharagpur;Indian Institute of Technology-Kharagpur
Venue:
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Year:
2005

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Abstract

A single chip frequency synthesizer compliant with the ZigBee standard is designed in a standard 0.18µ CMOS process. Integer N topology is chosen for the implementation. Synthesizer consists of third order passive loop filter; a CML based programmable frequency divider, a standard tristate PFD, a switch on source topology based charge pump and an on chip quadrature VCO. Simulated settling time is 300µsec. Synthesizer consumes 22mW of power at supply voltage of 1.8V and occupies an active area of mm虏.