Fully Integrated CMOS Frequency Synthesizer for ZigBee Applications
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Low power high data rate wireless endoscopy transceiver
Microelectronics Journal
Design and modelling of a multi-standard fractional PLL in CMOS/SOI technology
Microelectronics Journal
ASAP '07 Proceedings of the 2007 IEEE International Conference on Application-Specific Systems, Architectures and Processors
Low-power/low-voltage RF microsystems for wireless sensors networks
Microelectronics Journal
A fully integrated CMOS voltage regulator for supply-noise-insensitive charge pump PLL design
Microelectronics Journal
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The ultra-low power frequency synthesizer for the transceivers used in the application of Medical Implantable Communication Services (MICS) is presented. The MICS band is from 402 to 405MHz. Each channel spacing is 300kHz. Integer-N architecture is used to implement the frequency synthesizer. The post layout simulations show that the total power consumption of the system is less than 260@mW at 1.2V power supply. The gains of the charge pump and voltage controlled oscillator (VCO) are 0.18@mA/rad and 50MHz/V, respectively. The standard 300kHz external clock is used as the reference. The design is carried out in the IBM 90nm 9LPRF CMOS technology.