Design and modelling of a multi-standard fractional PLL in CMOS/SOI technology

Authors:
Gilles Jacquemod;Lionel Geynet;Benjamin Nicolle;Emeric de Foucauld;William Tatinian;Pierre Vincent
Affiliations:
LEAT, UMR CNRS-UNSA 6071, Sophia Antipolis, France;LEAT, UMR CNRS-UNSA 6071, Sophia Antipolis, France and CEA/LETI, Grenoble, France;LEAT, UMR CNRS-UNSA 6071, Sophia Antipolis, France and Mentor Graphics, Meudon La Forêt, France;CEA/LETI, Grenoble, France;LEAT, UMR CNRS-UNSA 6071, Sophia Antipolis, France;CEA/LETI, Grenoble, France
Venue:
Microelectronics Journal
Year:
2008

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Abstract

This paper deals with the design of a fractional PLL for wireless multi-standard applications. This circuit has been produced using CMOS/SOI technology, with body voltage to control power consumption and phase noise performance. Five standards are covered by this structure: GSM (900MHz), DCS (1.8GHz), Bluetooth (2.45GHz) and 802.11a (5.8GHz). Based on multi-engine simulators, associated with a hierarchical models library, a virtual RF system platform, which allows designing complex SoCs, is also presented. The PLL, including digital and analogue parts, constitutes a very good benchmark to validate this platform.