Variation-aware clock network design methodology for ultra-low voltage (ULV) circuits

Authors:
Xin Zhao;Jeremy R. Tolbert;Chang Liu;Saibal Mukhopadhyay;Sung Kyu Lim
Affiliations:
Georgia Institute of Technology, Atlanta, USA;Georgia Institute of Technology, Atlanta, USA;Georgia Institute of Technology, Atlanta, USA;Georgia Institute of Technology, Atlanta, USA;Georgia Institute of Technology, Atlanta, USA
Venue:
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Year:
2011

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Abstract

This paper presents a design methodology for robust and low-energy clock networks for ultra-low voltage (ULV) circuits. We show that both clock slew and skew play important roles in achieving high maximum operating frequency (Fmax) and low clock energy in ULV circuits. In addition, clock networks in ULV circuits are highly sensitive to process variations. We propose a variation-aware methodology that controls both clock skew and slew to maximize Fmax and minimize clock power. Experimental results show that our clock network design method achieves lower energy (more than 20% savings) at comparable or even higher Fmax compared with the existing methods.