Slew-aware clock tree design for reliable subthreshold circuits
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Variation-aware clock network design methodology for ultra-low voltage (ULV) circuits
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
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This paper presents an accurate and fully analytical model of delay in subthreshold inverters. The model characterizes the direct connection between the input slew and output delay. It is also capable of predicting the signal slew at the inverter output. Delay and slew prediction models are used to compute delay and understand slew propagation in an inverter chain. These models can also provide insight into skew analysis of subthreshold clock networks. Variability analyses across power supply and threshold changes ensure the accuracy of the model.