Variations-aware low-power design and block clustering with voltage scaling

Authors:
Navid Azizi;Muhammad M. Khellah;Vivek K. De;Farid N. Najm
Affiliations:
Department of Electrical Engineering, University of Toronto, Markham, ON, Canada;Circuits Research Laboratory, Intel Corporation, Hillsboro, OR;Corporate Technology Group, Intel Corporation, Hillsboro, OR;Electrical and Computer Engineering Department, University of Toronto, Toronto, ON, Canada
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2007

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Abstract

We present a new methodology which takes into consideration the effect of within-die (WID) process variations on a low-voltage parallel system. We show that in the presence of process variations one should use a higher supply voltage than would otherwise be predicted to minimize the power consumption of a parallel systems. Previous analyses, which ignored WID process variations, provide a lower nonoptimal supply voltage which can underestimate the energy/operation by 8.2×. We also present a novel technique to limit the effect of temperature variations in a parallel system. As temperatures increases, the scheme reduces the power increase by 43% allowing the system to remain at it's optimal supply voltage across different temperatures. To further limit the effect of variations, and allow for a reduced power consumption, we analyzed the effects of clustering. It was shown that providing different voltages to each cluster can provide a further 10% reduction in energy/operation to a low-voltage parallel system, and that the savings by clustering increase as technology scales.