Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Statistical clock skew modeling with data delay variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Analysis and mitigation of variability in subthreshold design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Ultra-low-power DLMS adaptive filter for hearing aid applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance enhancement of subthreshold circuits using substrate biasing and charge-boosting buffers
Proceedings of the 20th symposium on Great lakes symposium on VLSI
A data capturing method for buses on chip
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Ultra-low-power signaling challenges for subthreshold global interconnects
Integration, the VLSI Journal
Interconnect optimization to enhance the performance of subthreshold circuits
Microelectronics Journal
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This paper describes an interconnect technique for subthreshold circuits to improve global wire delay and reduce the delay variation due to process-voltage-temperature (PVT) fluctuations. By internally boosting the gate voltage of the driver transistors, operating region is shifted from subthreshold region to super-threshold region enhancing performance and improving tolerance to PVT variations. Simulations of a clock distribution network using the proposed driver shows a 66%-76% reduction in 3σ clock skew value and 84%-88% reduction in clock tree delay compared to using conventional drivers. A 0.4-V test chip has been fabricated in a 0.18-µm 6-metal CMOS process to demonstrate the effectiveness of the proposed scheme. Measurement results show 2.6 × faster switching speed and 2.4 × less delay sensitivity under temperature variations.