Buffer insertion with accurate gate and interconnect delay computation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A two moments RC delay metric for performance optimization
ICCAD '00 Proceedings of the 2000 international conference on Computer-aided design
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Variational delay metrics for interconnect timing analysis
Proceedings of the 41st annual Design Automation Conference
A Probabilistic Approach to Buffer Insertion
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Buffer Insertion Considering Process Variation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the 2005 international symposium on Physical design
Probabilistic evaluation of solutions in variability-driven optimization
Proceedings of the 2006 international symposium on Physical design
Fast min-cost buffer insertion under process variations
Proceedings of the 44th annual Design Automation Conference
Variability aware low-power delay optimal buffer insertion for global interconnects
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE system-on-chip conference
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Abstract-In this work we investigate the buffer insertion problem under process variations. Sub 100-nm fabrication process causes significant variations on many design parameters. We propose a probabilistic buffer insertion method assuming variations on both interconnect and buffer parameters and consider their correlations due to common sources of variation. Our proposed method is compatible with the more accurate D2M wire-delay model, as well as the Elmore delay model. In addition, a probabilistic pruning criterion is proposed to evaluate potential solutions, while considering their correlations. Experimental results demonstrate that considering correlations using the more accurate D2M delay model results in meeting the timing constraint with an average probability of 0.63. However probabilistic buffer insertion ignoring correlations and deterministic methods, meet the timing constraint with an average probability of 0.25 and 0.19 respectively.