Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling

Authors:
Jeng-Liang Tsai;Charlie Chung-Ping Chen
Affiliations:
University of Wisconsin-Madison, Madison, WI;National Taiwan University, Taipei, Taiwan
Venue:
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Year:
2005

Citing 4
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Abstract

Zero-skew clock-tree with minimum clock-delay is preferable due to its low unintentional and process-variation induced skews. We propose a zero-skew buffered clock-tree synthesis flow and a novel algorithm that enables clock-tree optimization throughout the full zero-skew design-space by considering simultaneous buffer-insertion, buffer-sizing, and wire-sizing. For an industrial clock-tree with 3101 sink nodes, our algorithm achieves up to 45X clock-delay improvement and up to 23% power reduction compared with its initial routing.