Closed-form delay and crosstalk models for RLC on-chip interconnects using a matrix rational approximation

Authors:
Sourajeet Roy;Anestis Dounavis
Affiliations:
Department of Electrical and Computer Engineering, University of Western Ontario, London, ON, Canada;Department of Electrical and Computer Engineering, University of Western Ontario, London, ON, Canada
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2009

Citing 15
Cited 0

Analysis of Multiconductor Transmission Lines

Analysis of Multiconductor Transmission Lines
Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects

Proceedings of the 41st annual Design Automation Conference
Analytical models and algorithms for the efficient signal integrity verification of inductance-effect-prominent multicoupled VLSI circuit interconnects

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analytical modeling of crosstalk noise waveforms using Weibull function

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An analytical delay model for RLC interconnects

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PRIMA: passive reduced-order interconnect macromodeling algorithm

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Equivalent Elmore delay for RLC trees

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DTT: direct truncation of the transfer function - an alternative to moment matching for tree structured interconnect

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis of on-chip inductance effects for distributed RLC interconnects

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Generalized traveling-wave-based waveform approximation technique for the efficient signal integrity verification of multicoupled transmission line system

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An RLC interconnect model based on fourier analysis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Worst case crosstalk noise for nonswitching victims in high-speed buses

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling and analysis of crosstalk noise in coupled RLC interconnects

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analytical model for crosstalk and intersymbol interference in point-to-point buses

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analytical CAD Models for the Signal Transients and Crosstalk Noise of Inductance-Effect-Prominent Multicoupled Interconnect Lines

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.03

Visualization

Abstract

In this paper, a closed-form matrix rational-approximation algorithm is proposed to efficiently model the delay and crosstalk noise of coupled RLC on-chip interconnects. A key feature of the proposed algorithm is that, for any rational order, the approximation is obtained analytically in terms of predetermined coefficients and the per-unit-length parameters. As a result, the proposed method is not limited to fixed number of poles and provides a mechanism to increase the accuracy for cases when inductive effects are significant, the length of the line increases, or when the rise time of the signal becomes sharper. An error criterion is provided to select the order of approximation. The algorithm is tested for various single- and coupled-interconnect scenarios. The 50% delay and overshoot results match that of SPICE with less than 2% average error. The crosstalk results also accurately match those of SPICE with less than 4%average error.