Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computer Methods for Circuit Analysis and Design
Computer Methods for Circuit Analysis and Design
Invited Talk: Long Lossy Lines (L3) and Their Impact Upon Large Chip Performance
IPDI '98 Proceedings of the IEEE Symposium on IC/Package Design Integration
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis of on-chip inductance effects for distributed RLC interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis of interconnect networks using complex frequency hopping (CFH)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
EM Wave Coupling Noise Modeling Based on Chebyshev Approximation and Exact Moment Formulation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Information theoretic approach to address delay and reliability in long on-chip interconnects
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Data handling limits of on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Robust interconnect communication capacity algorithm by geometric programming
Proceedings of the 2009 international symposium on Physical design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient delay and crosstalk modeling of RLC interconnects using delay algebraic equations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The closed-form expressions of distributed RLC interconnects are proposed for analysis of on-chip inductance effects in order to insert optimally the repeaters. The transfer function of a circuit with driver-interconnect-load structure is approximated by the 5th order rational functions. The step responses computed by using the proposed expressions give the good agreement with the SPICE simulations.