A wide frequency range surface integral formulation for 3-D RLC extraction
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Proceedings of the 38th annual Design Automation Conference
How to efficiently capture on-chip inductance effects: introducing a new circuit element K
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Proceedings of the 40th annual Design Automation Conference
An analytical delay model for RLC interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient techniques for 3-D impedance extraction using mixed boundary element method
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
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A direct boundary element method (BEM) was recently proposed for inductance extraction. Though faster than other volume integral methods, it still suffers from as many as 7N unknowns where N is the number of panels. A mixed BEM for inductance extraction is proposed in this paper, which combines indirect boundary integral equations (BIEs) of double layer potentials within conductors and direct BIEs within dielectric (between conductors). With this mixed BEM, the number of unknowns is remarkably cut down from 7N to 4N, and correspondingly, the CPU time spent on solving the linear system decreases greatly. Two interconnect structures are simulated to demonstrate the validity of this method.