DAC '98 Proceedings of the 35th annual Design Automation Conference
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A decoupling method for analysis of coupled RLC interconnects
Proceedings of the 12th ACM Great Lakes symposium on VLSI
An analytical delay model for RLC interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On integrating power and signal routing for shield count minimization in congested regions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simultaneous shield and repeater insertion
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Exploiting parity computation latency for on-chip crosstalk reduction
IEEE Transactions on Circuits and Systems II: Express Briefs
Resource based optimization for simultaneous shield and repeater insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Semi-random net reordering for reducing timing variations and improving signal integrity
Microelectronics Journal
Fast and efficient extraction algorithm for high-speed interconnects with arbitrary boundaries
The Journal of Supercomputing
Data bus swizzling in TSV-based three-dimensional integrated circuits
Microelectronics Journal
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On-chip interconnect delay and crosstalk noise have become significant bottlenecks in the performance and signal integrity of deep submicrometer VLSI circuits. A crosstalk noise model for both identical and nonidentical coupled resistance-inductance-capacitance (RLC) interconnects is developed based on a decoupling technique exhibiting an average error of 6.8% as compared to SPICE. The crosstalk noise model, together with a proposed concept of effective mutual inductance, is applied to evaluate the effectiveness of the shielding technique.