Analysis of glitch power dissipation in CMOS ICs
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Interconnect coupling noise in CMOS VLSI circuits
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Delay and noise estimation of CMOS logic gates driving coupled resistive-capacitive interconnections
Integration, the VLSI Journal
Simultaneous shield insertion and net ordering under explicit RLC noise constraint
Proceedings of the 38th annual Design Automation Conference
Interconnect Optimization Strategies for High-Performance VLSI Designs
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Controlling Inductive Coupling in Wide Global Signal Busses Through Swizzling
Analog Integrated Circuits and Signal Processing
Computer Architecture, Fourth Edition: A Quantitative Approach
Computer Architecture, Fourth Edition: A Quantitative Approach
Fundamentals of Electric Circuits
Fundamentals of Electric Circuits
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Crosstalk modeling for coupled RLC interconnects with application to shield insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Shielding Methodologies in the Presence of Power/Ground Noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The purpose of this paper is to efficiently exploit swizzling in reducing coupling noise between the bit lines of a TSV-based data bus in three-dimensional integrated circuits. The core concept of swizzling is to distribute the noise of an aggressor to all victims, rather than concentrating on the nearest victim. Based on this principle, an optimal swizzling pattern, which achieves an equal distribution of the coupling impedance, is proposed. The efficiency of this optimal pattern is demonstrated through comparison to no swizzling and two other swizzling patterns while considering different TSV diameters, aspect ratios, pitches, and transition times of the aggressor signal. A circuit model of a TSV-based 3-D data bus is evaluated in HSPICE with each TSV modeled as an RLC impedance. A maximum reduction of 51% in peak coupling noise is achieved.