IEEE Transactions on Computers
Computing optimal clock schedules
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
On switch factor based analysis of coupled RC interconnects
Proceedings of the 37th Annual Design Automation Conference
Deep Sub-Micron Static Timing Analysis in Presence of Crosstalk
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
On-chip inductance cons and pros
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An analytical delay model for RLC interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Semi-random net reordering for reducing timing variations and improving signal integrity
Microelectronics Journal
Signal integrity and propagation delay analysis using FDTD technique for VLSI interconnects
Journal of Computational Electronics
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With the continuous increase of circuit density, interconnect length, and aspect ratio, the influence of capacitive and inductive coupling on timing characteristics of integrated circuits has become very critical. In this paper, the effects of capacitive and inductive coupling on delay uncertainty and clock skew have been analyzed. Analytical observations and simulation results show that coupling capacitance and mutual inductance have opposite impacts on delay and clock skew variations. It is illustrated that while capacitive coupling worsens both variations, growing inductive coupling can actually counter-balance the negative impacts to some degree.