A New Approach to Pipeline FFT Processor
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Efficient Implementation of Rotation Operations for High Performance QRD-RLS Filtering
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
A Cordic-Based Processor Extension for Scalar and Vector Processing
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 13 - Volume 14
Novel design of multiplier-less FFT processors
Signal Processing
Pruning fast Fourier transform algorithm design using group-based method
Signal Processing
Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations
IEEE Transactions on Computers
An Efficient Method for Improving Reliability of a Pipeline FFT
IEEE Transactions on Computers
A BCD-based architecture for fast coordinate rotation
Journal of Systems Architecture: the EUROMICRO Journal
Long-Point FFT Processing Based on Twiddle Factor Table Reduction
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A Parallel Double-Step CORDIC Algorithm for Digital Down Converter
CNSR '09 Proceedings of the 2009 Seventh Annual Communication Networks and Services Research Conference
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Pipeline architectures for radix-2 new Mersenne number transform
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2008 custom integrated circuits conference (CICC 2008)
50 years of CORDIC: algorithms, architectures, and applications
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A high throughput FFT processor with no multipliers
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Algorithms and pipeline architectures for 2-D FFT and FFT-like transforms
Digital Signal Processing
CORDIC architectures: a survey
VLSI Design
Function approximation on decimal operands
Digital Signal Processing
A CORDIC processor for FFT computation and its implementation using gallium arsenide technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reduced Memory and Low Power Architectures for CORDIC-based FFT Processors
Journal of Signal Processing Systems
An iterative method for improving decimal calculations on computers
Mathematical and Computer Modelling: An International Journal
International Journal of Reconfigurable Computing
Leading One Detection Hyperbolic CORDIC with Enhanced Range of Convergence
Journal of Signal Processing Systems
Pipelined parallel FFT architectures via folding transformation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Pipelined radix-2k feedforward FFT architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The CORDIC iteration is applied to several Fourier transform algorithms. The number of operations is found as a function of transform method and radix representation. Using these representations, several hardware configurations are examined for cost, speed, and complexity tradeoffs. A new, especially attractive FFT computer architecture is presented as an example of the utility of this technique. Compensated and modified CORDIC algorithms are also developed.