Reduced Memory and Low Power Architectures for CORDIC-based FFT Processors

Authors:
Erdal Oruklu;Xin Xiao;Jafar Saniie
Affiliations:
Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, USA 60616;Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, USA 60616;Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, USA 60616
Venue:
Journal of Signal Processing Systems
Year:
2012

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Abstract

This paper presents a pipelined, reduced memory and low power CORDIC-based architecture for fast Fourier transform implementation. The proposed algorithm utilizes a new addressing scheme and the associated angle generator logic in order to remove any ROM usage for storing twiddle factors. As a case study, the radix-2 and radix-4 FFT algorithms have been implemented on FPGA hardware. The synthesis results match the theoretical analysis and it can be observed that more than 20% reduction can be achieved in total memory logic. In addition, the dynamic power consumption can be reduced by as much as 15% by reducing memory accesses.