A Low-Power and Domain-Specific Reconfigurable FFT Fabric for System-on-Chip Applications
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Domain Specific Reconfigurable Processing Core Architecture for Digital Filtering Applications
Journal of VLSI Signal Processing Systems
Design of a high performance FFT processor based on FPGA
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
VLSI implementation of programmable FFT architectures for OFDM communication system
Proceedings of the 2006 international conference on Wireless communications and mobile computing
Proceedings of the conference on Design, automation and test in Europe
Generic multiphase software pipelined partial FFT on instruction level parallel architectures
IEEE Transactions on Signal Processing
A generalized mixed-radix algorithm for memory-based FFT processors
IEEE Transactions on Circuits and Systems II: Express Briefs
Reduced Memory and Low Power Architectures for CORDIC-based FFT Processors
Journal of Signal Processing Systems
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The memory organization of FFT processors is considered. The new memory addressing assignment allows simultaneous access to all the data needed for butterfly calculations. The advantage of this memory addressing scheme lies in the fact that it reduces the delay of address generation nearly by half compared to existing ones