Efficient VLSI architectures for fast computation of the discreteFourier transform and its inverse
IEEE Transactions on Signal Processing
A hardware efficient control of memory addressing forhigh-performance FFT processors
IEEE Transactions on Signal Processing
An effective memory addressing scheme for FFT processors
IEEE Transactions on Signal Processing
| Hi-index | 0.00 |
Two programmable FFT processors for OFDM (Orthogonal Frequency Division Multiplex) communication systems are presented in this paper. Coolay-Tukey radix-2/4/8 algorithm and mixed-radix-2/22/23 are employed in the pipelined SDF (Single-path Delay Feedback) architecture and pipelined MDC (Multiple-Path Delay Commutator) shared-memory architecture, respectively. The size of FFT processors with power of 2 can be programmable in the range between 64 and 8192. Based on the programmable SDF architecture, an FFT processor with 64/128-point has been implemented under the TSMC 0.35mm CMOS technology. Its core area is 1.6*1.6mm2 and the power consumption is 340mW. Moreover, a simple addressing scheme for pipelined MDC shared-memory architecture with mixed-radix algorithm is also proposed to achieve the programmable object. It can provide a simple control circuit for memory addressing generation, and the mixed-radix butterfly sequence can be automatically generated by way of simple counter. In addition, for the N-point FFT processor, only N/8 coefficients should be stored in the VLSI implementation, therefore, the ROM size and the FFT processor area are reduced. According to the simple control scheme and smaller memory size, the low-power VLSI architecture can be achieved. Furthermore, the architecture with the mixed-radix algorithm also enhances the speed in performing large-point FFT computations compared with the existing shared-memory architectures. Based on this architecture, not only high radix-23 butterfly is adopted to achieve the requirement of high throughput, but also low radix-22 or radix-2 butterfly is utilized to allow all of FFT calculation for N=2n. An VLSI architecture of 8192-point FFT processor with only power consumption of 890mW is also implemented to demonstrate the proposed method.