Very Fast Fourier Transform Algorithms Hardware for Implementation
IEEE Transactions on Computers
Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations
IEEE Transactions on Computers
Fourier Transform Computers Using CORDIC Iterations
IEEE Transactions on Computers
Optimizing energy to minimize errors in dataflow graphs using approximate adders
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
A low-power globally synchronous locally asynchronous FFT processor
HPCC'07 Proceedings of the Third international conference on High Performance Computing and Communications
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This paper presents a novel and hardware-efficient architecture for power-of-two FFT processors. The proposed design is based on the phase-amplitude splitting technique which converts a DFT to cyclic convolutions and additions. The cyclic convolutions are implemented with a filter-like structure and the additions are computed with several stages of butterfly processing units. The proposed architecture requires no multiplier, and comparisons with other designs show it can save up to 39% total equivalent gates for an 8-bit 16-point FPGA-based FFT processor.