Reconfigurable VLSI architecture for FFT processor

Authors:
Tze-Yun Sung;Hsi-Chin Hsin
Affiliations:
Department of Microelectronics Engineering, Chung Hua University, Hsinchu City, Taiwan;Department of Computer Science and Information Engineering, National United University, Miaoli, Taiwan
Venue:
MUSP'09 Proceedings of the 9th WSEAS international conference on Multimedia systems & signal processing
Year:
2009

Citing 7
Cited 0

Automatic Generation of Split-Radix 2-4 Parallel-Pipeline FFT Processors: Hardware Reconfiguration and Core Optimizations

PARELEC '06 Proceedings of the international symposium on Parallel Computing in Electrical Engineering
Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations

IEEE Transactions on Computers
Fourier Transforms in VLSI

IEEE Transactions on Computers
Fixed-Point Error Analysis of CORDIC Arithmetic for Special-Purpose Signal Processors

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
High-speed and low-power split-radix FFT

IEEE Transactions on Signal Processing
An approach to simplify the design of IFFT/FFT cores for OFDM systems

IEEE Transactions on Consumer Electronics
A Low Power and Small Area FFT Processor for OFDM Demodulator

IEEE Transactions on Consumer Electronics

Quantified Score

Hi-index	0.00

Visualization

Abstract

Detection of supported membranes with the acoustic sensor devices is an important objective of many existing nanotechnology needs. Surface acoustic wave (SAW)-based sensors belong to the leading group among acoustic sensors due to their considerable ...