Automatic Generation of Split-Radix 2-4 Parallel-Pipeline FFT Processors: Hardware Reconfiguration and Core Optimizations

Authors:
Alexander A. Petrovsky;Sergei L. Shkredov
Affiliations:
Bialystok Technical University, Poland;Belarusian State University of Informatics and Radioelectronics, Russia
Venue:
PARELEC '06 Proceedings of the international symposium on Parallel Computing in Electrical Engineering
Year:
2006

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Abstract

The results presented in the article are based on a methodology for automatic synthesis of real-time split radix 2-4 parallel-pipeline FFT-processors at structural level. The approach is oriented at reconfigurable FPGAaware design and allows taking into account real-time application restrictions (input data structure and format, operating frequency, transform size, overall throughput) as well as other design restrictions (CLB-count, area, power dissipation). The considered design examples prove method's good abilities for hardware optimization. Variants of split radix 2-4 computing element implementation are compared. Switching over from floating point arithmetics to fixed point data and the corresponding accuracy issues are considered.