Discrete-time signal processing (2nd ed.)
Discrete-time signal processing (2nd ed.)
A New Approach to Pipeline FFT Processor
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Some Results in Fixed-Point Fast Fourier Transform Error Analysis
IEEE Transactions on Computers
Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations
IEEE Transactions on Computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic IP generation of FFT/IFFT processors with word-length optimization for MIMO-OFDM systems
EURASIP Journal on Advances in Signal Processing - Special issue on quantization of VLSI digital signal processing systems
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Quickly and accurately predicting of the performance based on the requirements for IP-based system implementations optimizes design and reduces design time and overall cost. This study describes a novel hybrid method for the wordlength optimization of pipelined FFT processors that is the arithmetic kernel of OFDM-based systems. This methodology utilizes the rapid computing of statistical analysis and the accurate evaluation of simulation-based analysis to investigate a speedy optimization flow. A statistical error model for varying wordlengths of PE stages of an FFT processor was developed to support this optimization flow. Experimental results designate that the wordlength optimization employing the speedy flow reduces the percentage of the total area of the FFT processor that increases with an increasing FFT length. Finally, the proposed hybrid method requires shorter prediction time than the absolute simulation-based method does and achieves more accurate outcomes than a statistical calculation does.