Integration letter: Contributions to VLSI computational complexity theory from bounds on current density

Authors:
H. C. Card;W. Pries;R. D. McLeod
Affiliations:
-;-;-
Venue:
Integration, the VLSI Journal
Year:
1986

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Abstract

The grid models of VLSI algorithms embody the common assumption that time delays on wires of length L are O(log L). We show that the hierarchical model of driver circuitry responsible for this result is restricted, in its application to asymptotic complexity determinations, by the physical upper bound on current density in the wires for any VLSI technology. Unlike other alternative models of wire delay concerned with resistive properties of the wires or transmission line effects, there are no practical technological fixes for current density limits. It is suggested that the appropriate model for physically realizable VLSI algorithms should contain asymptotic wire delays that are Q(L).