IEEE Transactions on Computers
The VLSI Complexity of Sorting
IEEE Transactions on Computers
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The thesis is divided into two parts. In the first part, we describe and analyze several new VLSI layouts for the shuffle-exchange graph. These include:\ 1) an asymptotically optimal, (N /log N)-area layout for the N-node shuffle-exchange graph, and 2) several practical layouts for small shuffle-exchange graphs. The new layouts require substantially less area than previously known layouts and can serve as the basis for designing large scale shuffle-exchange chips. In the second part of the thesis, we develop general methods for proving lower bounds on the layout area, crossing number, bisection width and maximum edge length of VLSI networks. Among other things, we use these methods to find: 1) an N-node planar graph which has layout area (NlogN) and maximum edge length (N /log N), 2) an N-node graph with an O(N )-separator which has layout area (Nlog N) and maximum edge length (N logN/loglogN), and 3) an -node graph with an O(N )-separator (for