A low area pipelined FFT processor for OFDM based systems

Authors:
Qihui Zhang;Nan Meng
Affiliations:
School of Physics and Electronics, Henan University, Kaifeng, China;School of Electronic Engineering, Beijing University of Posts and Telecommunications, Beijing, China
Venue:
WiCOM'09 Proceedings of the 5th International Conference on Wireless communications, networking and mobile computing
Year:
2009

Citing 3
Cited 0

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Abstract

In this paper, a memory-based architecture of FFT processor customized for OFDM-based communication systems is presented. For the finite word length effects consideration of the Decimation In Time (DIT) and Decimation In Frequency (DIF) algorithms, DIF algorithm is selected in our design. Complex multiplication is the main design key in the FFT butterfly transform, a simplification of the complex multiplication is performed by an improved algorithm, and then a pipelined butterfly processing element (BPE) is described accordingly. We also adopt an efficient memory access scheme to achieve considerable power consumption and cost reduction. Finally, a VLSI implementation of radix-2 DIF FFT processor is carried out in a 0.13 µm CMOS technology. The estimated area and power consumption of the proposed FFT processor are 2.96 mm2 and 268 mW respectively. The proposed low area pipelined FFT processor is multimode/multistandard and can be suitably applied in WALN, DVB-T, ADSL and the other OFDM-based multicarrier systems.