A New FFT Architecture and Chip Design for Motion Compensation based on Phase Correlation
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
A novel memory-based FFT processor for DMT/OFDM applications
ICASSP '99 Proceedings of the Acoustics, Speech, and Signal Processing, 1999. on 1999 IEEE International Conference - Volume 04
A novel trellis-based searching scheme for EEAS-based CORDIC algorithm
ICASSP '01 Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference - Volume 02
A CORDIC processor for FFT computation and its implementation using gallium arsenide technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high performance parallel Radon based OFDM transceiver design and simulation
Digital Signal Processing
A low area pipelined FFT processor for OFDM based systems
WiCOM'09 Proceedings of the 5th International Conference on Wireless communications, networking and mobile computing
The performance of multiwavelets based OFDM system under different channel conditions
Digital Signal Processing
An energy-efficient partial FFT processor for the OFDMA communication system
IEEE Transactions on Circuits and Systems II: Express Briefs
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The technique of orthogonal frequency division multiplexing (OFDM) is famous for its robustness against frequency-selective fading channel. This technique has been widely used in many wired and wireless communication systems. In general, the fast Fourier transform (FFT) and inverse FFT (IFFT) operations are used as the modulation/demodulation kernel in the OFDM systems, and the sizes of FFT/IFFT operations are varied in different applications of OFDM systems. In this paper, we design and implement a variable-length prototype FFT/IFFT processor to cover different specifications of OFDM applications. The cached-memory FFT architecture is our suggested VLSI system architecture to design the prototype FFT/IFFT processor for the consideration of low-power consumption. We also implement the twiddle factor butterfly processing element (PE) based on the coordinate rotation digital computer (CORDIC) algorithm, which avoids the use of conventional multiplication-and-accumulation unit, but evaluates the trigonometric functions using only add-and-shift operations. Finally, we implement a variable-length prototype FFT/IFFT processor with TSMC 0.35 µm 1P4M CMOS technology. The simulations results show that the chip can perform (64-2048)-point FFT/IFFT operations up to 80 MHz operating frequency which can meet the speed requirement of most OFDM standards such as WLAN, ADSL, VDSL (256 ∼ 2K), DAB, and 2k-mode DVB.