Quantifying and enhancing power awareness of VLSI systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
VLSI design of a variable-length FFT/IFFT processor for OFDM-based communication systems
EURASIP Journal on Applied Signal Processing
Architectures for dynamic data scaling in 2/4/8K pipeline FFT cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel generic fast Fourier transform pruning technique and complexity analysis
IEEE Transactions on Signal Processing
IEEE Transactions on Consumer Electronics
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In the orthogonal frequency-division multiple-access (OFDMA) communication system, resource allocation plays an important role in improving the transmission performance. The maximum spectral efficiency can be achieved through channel quality measurement, resource allocation, adaptive modulation, and so on. In this brief, we design a partial cached fast Fourier transform (FFT) processor that accounts for the distribution of allocated resources to the users of the OFDMA system. We also design a constellation- and power-aware twiddle-factor multiplier for the variable FFT length and modulation order. We implement a 128- to 1024-point mixed pipelined/cached-FFT processor using a 0.18-µm 1P6M CMOS technology. The chip measurement results show that its energy dissipation ranges from 0.09 to 1.90 nJ per FFT point and scales to the allocated resources in the OFDMA system.