Roundoff errors in block-floating-point systems
IEEE Transactions on Signal Processing
A 2K/8K mode small-area FFT processor for OFDM demodulation of DVB-T receivers
IEEE Transactions on Consumer Electronics
A Hardware Acceleration Platform for Digital Holographic Imaging
Journal of Signal Processing Systems
An energy-efficient partial FFT processor for the OFDMA communication system
IEEE Transactions on Circuits and Systems II: Express Briefs
A 2.4-GS/s FFT processor for OFDM-based WPAN applications
IEEE Transactions on Circuits and Systems II: Express Briefs
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This paper presents architectures for supporting dynamic data scaling in pipeline fast Fourier transforms (FFTs), suitable when implementing large size FFTs in applications such as digital video broadcasting and digital holographic imaging. In a pipeline FFT, data is continuously streaming and must, hence, be scaled without stalling the dataflow. We propose a hybrid floating-point scheme with tailored exponent datapath, and a co-optimized architecture between hybrid floating point and block floating point (BFP) to reduce memory requirements for 2-D signal processing. The presented co-optimization generates a higher signal-to-quantization-noise ratio and requires less memory than for instance convergent BFP. A 2048-point pipeline FFT has been fabricated in a standard-CMOS process from AMI Semiconductor (Lenart and Öwall, 2003), and a field-programmable gate array prototype integrating a 2-D FFT core in a larger design shows that the architecture is suitable for image reconstruction in digital holographic imaging.