An Area-Efficient Design of Variable-Length Fast Fourier Transform Processor
Journal of Signal Processing Systems
An FFT core for DVB-T/DVB-H receivers
VLSI Design
Low-complexity FFT/IFFT IP hardware macrocells for OFDM and MIMO-OFDM CMOS transceivers
Microprocessors & Microsystems
Architectures for dynamic data scaling in 2/4/8K pipeline FFT cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
STBC-OFDM downlink baseband receiver for mobile WMAN
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present a novel implementation for 2K/8K dual-mode FFT (fast Fourier transform) for OFDM (orthogonal frequency division multiplexing) of DVB-T (digital video broadcasting terrestrial) receivers. Besides pipelining the FFT to reduce the area and enhance the data throughput, SDF (single-path delay feedback) butterfly units for radix-2 and radix-4 processing are adopted to resolve the power consumption difficulty and the P&R (place and route) problem. The SRAM is used in the butterfly units to relax the auto-refreshing requirement if DRAM is used such that not only is the dynamic power saved, the timing control is also less stingy. The 2K/8K FFT comprises 5/6 cascaded stages of radix-4 and one stage of radix-2 butterfly units. The proposed design is carried out by 0.35 μm 2P4M CMOS process to verify the high processing 8 MHz rate with power dissipation as low as 535 mW at a 16 MHz system clock.