Discrete-time signal processing (2nd ed.)
Discrete-time signal processing (2nd ed.)
A New Approach to Pipeline FFT Processor
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
A pipelined architecture for the multidimensional DFT
IEEE Transactions on Signal Processing
A 2K/8K mode small-area FFT processor for OFDM demodulation of DVB-T receivers
IEEE Transactions on Consumer Electronics
Fully Systolic FFT Architecture for Giga-sample Applications
Journal of Signal Processing Systems
Low-Power Application-Specific Processor for FFT Computations
Journal of Signal Processing Systems
CORDIC-Based VLSI Architecture for Implementing Kaiser-Bessel Window in Real Time Spectral Analysis
Journal of Signal Processing Systems
| Hi-index | 0.00 |
Fast Fourier transform (FFT) plays an important role in the orthogonal frequency division multiplexing (OFDM) communication systems. In this paper, we propose an area-efficient design of variable-length FFT processor which can perform various FFT lengths of 512/1,024/2,048/4,096/8,192 points used in OFDM-based communication systems, such as digital audio broadcasting (DAB), digital video broadcasting-terrestrial (DVB-T) and digital video broadcasting-handheld (DVB-H). To reduce computational complexity and chip area, we develop a new variable-length FFT architecture by devising a mixed-radix algorithm that consist of radix-2, radix-22 and radix-2/4/8 algorithms and optimizing the realization by substructure sharing. Based on this architecture, an area-efficient design of variable-length FFT processor is presented. By synthesized using the UMC 0.18 μm process, the area of the processor is 2.9 mm2 and the 8,192-point FFT can be performed correctly up to 50 MHz with power consumption 823 mW under a 1.8 V supply voltage.