VLSI design of a variable-length FFT/IFFT processor for OFDM-based communication systems
EURASIP Journal on Applied Signal Processing
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Details of a new low power FFT processor for use in digital televison applications are presented. This has been fabricated using a 0.6 um CMOS technology and can perform a 64 point complex forward or inverse FFT on real-time video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8x8 mm2 and dissipates 1W. Its performance, in terms of computational rate per area per watt, is significantly higher than previously reported devices, leading to a cost-effective silicon solution for high quality video processing applications. This is the result of using a novel VLSI architecture which has been derived from a first principles factorization of the DFT matrix and tailored to a direct silicon implementation.