VLSI design of a variable-length FFT/IFFT processor for OFDM-based communication systems
EURASIP Journal on Applied Signal Processing
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This paper presents a novel VLSI architecture for computing the N-point discrete Fourier transform (DFT) based on a radix-2 fast algorithm, where N is a power of two. The architecture consists of one complex multiplier, two complex adders, and some special memory units. It can compute one transform sample every log/sub 2/N+1 clock cycles in average. For the case of N=512, the chip area required is about 5742/spl times/5222 /spl mu/m/sup 2/ and the throughput is up to 4 M transform samples per second under 0.6 /spl mu/m CMOS technology. Such area-time performance makes the proposed design rather attractive for use in long-length DFT applications, such as ADSL and OFDM systems.