Fast: FFT ASIC automated synthesis

Authors:
L. Fanucci;M. Forliti;P. Terreni
Affiliations:
Centro Studio Metodi e Dispositivi per Radiotrasmissioni, National Research Council, Via Diotisalvi 2, I-56122 Pisa, Italy;Department of Information Engineering, University of Pisa, Via Diotisalvi 2, I-56122 Pisa, Italy;Department of Information Engineering, University of Pisa, Via Diotisalvi 2, I-56122 Pisa, Italy
Venue:
Integration, the VLSI Journal
Year:
2002

Citing 4
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Abstract

In this paper, an automated design method for the synthesis of a high-throughput fast Fourier transform (FFT) ASIC is presented, applicable to any power-of-two FFT sizes. The method is based on a C++ program named FAST which has been developed as a friendly dialogue-window interface to help the designer, first to obtain a bit-true FFT architecture to attain the desired precision performance and then to derive validated gate-level netlists for the selected silicon technology. As a result, a substantial reduction of the design time is achieved. The FFT processor implements a mixed 2/4 radix algorithm with a Cascade Bi and Jones architecture. The relevant VLSI design is based on a parametric, highly flexible VHDL description created using a design-reuse approach. According to the FAST methodology, two prototypes (64- and 1024-point FFT processors) have been developed resulting very interesting in terms of hardware complexity and precision performance when compared with state of the art; in particular, the 64-point FFT processor exhibits an area-time product nearly 30% lower than previous works following automatic-design methodologies.