ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Fault-secure algorithms for multiple-processor systems
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Algorithm-Based Fault Detection for Signal Processing Applications
IEEE Transactions on Computers
Algorithm-Based Error-Detection Schemes for Iterative Solution of Partial Differential Equations
IEEE Transactions on Computers
Algorithm-Based Fault Tolerant Synthesis for Linear Operations
IEEE Transactions on Computers
Algorithm-Based Fault Location and Recovery for Matrix Computations on Multiprocessor Systems
IEEE Transactions on Computers
Soft digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Efficient FFT network testing and diagnosis schemes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal Design of Checks for Error Detection and Location in Fault-Tolerant Multiprocessor Systems
IEEE Transactions on Computers
Diagnosability and Diagnosis of Algorithm-Based Fault-Tolerant Systems
IEEE Transactions on Computers
Algorithm-Based Fault Tolerance for FFT Networks
IEEE Transactions on Computers
An Efficient Algorithm-Based Concurrent Error Detection for FFT Networks
IEEE Transactions on Computers
A Novel Concurrent Error Detection Scheme for FFT Networks
IEEE Transactions on Parallel and Distributed Systems
Partitioned Encoding Schemes for Algorithm-Based Fault Tolerance in Massively Parallel Systems
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
Cost analysis of a new algorithmic-based soft-error tolerant architecture
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
An Algorithm-Based Error Detection Scheme for the Multigrid Method
IEEE Transactions on Computers
Design-for-testability and fault-tolerant techniques for FFT processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On concurrent error location and correction of FFT networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fault tolerant preconditioned conjugate gradient for sparse linear system solution
Proceedings of the 26th ACM international conference on Supercomputing
| Hi-index | 15.01 |
A method is proposed for achieving fault tolerance by introducing a redundant stage for a special-purpose fast Fourier transform (FFT) processor. A concurrent error-detection technique, called recomputing by alternate path, is used to detect errors during normal operation. Once an error is detected, a faulty butterfly can be located with log (N+5) additional cycles. The method has 100% detection and location capability, regardless of the magnitude of the roundoff errors. A gracefully degraded reconfiguration using a redundant stage is introduced. This technique ensures a high improvement in reliability and availability. Hardware overhead is O(1/log N) with some additional comparators and switches. The method can be applied to other algorithms implementable on the butterfly structure.