Cost analysis of a new algorithmic-based soft-error tolerant architecture

Authors:
Y. Blaquiere;G. Gagne;Y. Savaria;C. Evequoz
Affiliations:
-;-;-;-
Venue:
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Year:
1995

Citing 6
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Abstract

A new ABFT architecture is proposed to tolerate multiple soft-errors with low overheads. It memorizes operands on a stack upon error detection and corrects errors by recomputing. This allows uninterrupted input data streams to lie processed without data loss.