Bounds on Algorithm-Based Fault Tolerance in Multiple Processor Systems
IEEE Transactions on Computers - The MIT Press scientific computation series
VLSI array processors
IEEE Transactions on Computers
A Fault-Tolerant FFT Processor
IEEE Transactions on Computers
A Fault-Tolerant Systolic Sorter
IEEE Transactions on Computers
Fault-Tolerant Matrix Triangularizations on Systolic Arrays
IEEE Transactions on Computers
Real-Number Codes for Fault-Tolerant Matrix Operations on Processor Arrays
IEEE Transactions on Computers
Algorithm-Based Fault Detection for Signal Processing Applications
IEEE Transactions on Computers
Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor
IEEE Transactions on Computers
What every computer scientist should know about floating-point arithmetic
ACM Computing Surveys (CSUR)
Ordered fast Fourier transforms on a massively parallel hypercube multiprocessor
Journal of Parallel and Distributed Computing
Fast Transforms: Algorithms, Analyses, Applications
Fast Transforms: Algorithms, Analyses, Applications
The Design of Fault-Tolerant Linear Digital State Variable Systems: Theory and Techniques
IEEE Transactions on Computers
Synthesis of Algorithm-Based Fault-Tolerant Systems from Dependence Graphs
IEEE Transactions on Parallel and Distributed Systems
Error Control Coding, Second Edition
Error Control Coding, Second Edition
Graph Theory With Applications
Graph Theory With Applications
Optimal real number codes for fault tolerant matrix operations
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
Algorithm-based recovery for iterative methods without checkpointing
Proceedings of the 20th international symposium on High performance distributed computing
Periodic and non-concurrent error detection and identification in one-hot encoded FSMs
Automatica (Journal of IFAC)
Fault tolerant preconditioned conjugate gradient for sparse linear system solution
Proceedings of the 26th ACM international conference on Supercomputing
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High-level synthesis is becoming more important in practical design environments to meet new system requirements and, increasingly, fault tolerance is one especially because of high-speed and low power demands. This paper explores several basic aspects of low-cost fault tolerant synthesis for practical linear systems. It deals with practical design constraints that require basic operations to be only performed by a limited processing resources and do not normally assign each operation a separate processing resource. Two core issues, partitioning and allocation, for fault tolerant synthesis are examined. Results demonstrate a high-level abstraction and framework for fault tolerant synthesis which is almost totally independent of the physical hardware implementation. Issues in designing 1-fault detectable FFT system are considered in detail to illustrate the significance and effects of fault tolerant synthesis schemes. Our ultimate goal is to incorporate these techniques in future automated design tools so that fault tolerance features can be part of the design options.