Concurrent Fault Detection in Microprogrammed Control Units
IEEE Transactions on Computers
Finite Field Fault-Tolerant Digital Filtering Architectures
IEEE Transactions on Computers
Optimized Synthesis of Concurrently Checked Controllers
IEEE Transactions on Computers
Fault-tolerant computation using algebraic homomorphisms
Fault-tolerant computation using algebraic homomorphisms
Algorithm-Based Fault Tolerant Synthesis for Linear Operations
IEEE Transactions on Computers
Generalized Algorithm-Based Fault Tolerance: Error Correction via Kalman Estimation
IEEE Transactions on Computers
Concurrent Error Detection in Sequential Circuits Using Convolutional Codes
AAECC-9 Proceedings of the 9th International Symposium, on Applied Algebra, Algebraic Algorithms and Error-Correcting Codes
Algorithm-Based Fault Tolerance for Matrix Operations
IEEE Transactions on Computers
Coding Techniques for Failure- Tolerant Counters
IEEE Transactions on Computers
Redundancy by Coding Versus Redundancy by Replication for Failure-Tolerant Sequential Circuits
IEEE Transactions on Computers
IEEE Transactions on Information Theory
| Hi-index | 22.14 |
State-transition faults in digital sequential systems, such as finite-state logic controllers, have traditionally been handled by embedding the given system into a larger one, in a way that preserves the state evolution of the original system while enabling an external mechanism to concurrently perform checks to detect, identify and correct errors. In this paper, we develop a methodology for systematically constructing embeddings of one-hot encoded finite-state machines (FSMs) in a way that allows the external mechanism to capture transient state-transition faults via checks that are performed in a non-concurrent manner (e.g., periodically). More specifically, by employing coding techniques over finite fields, we completely characterize an appropriate class of redundant FSM embeddings and its corresponding non-concurrent error-detecting/identifying capabilities. These embeddings can be used to construct a redundant version of the given one-hot encoded FSM so that the external mechanism can detect and identify errors due to past state-transition faults based on an analysis of the current, possibly corrupted FSM state. As a result, the proposed error detection and identification approach relaxes the stringent requirements on the reliability of the checker and avoids the slowdown associated with concurrent checking.