Probability of State Transition Errors in a Finite State Machine Containing Soft Failures
IEEE Transactions on Computers
Realization of Fault-Tolerant Machines Linear Code Application
IEEE Transactions on Computers
Fault-Tolerant Asynchronous Networks
IEEE Transactions on Computers
Realization of fault-tolerant and Fail-Safe sequential machines
IEEE Transactions on Computers
Periodic and non-concurrent error detection and identification in one-hot encoded FSMs
Automatica (Journal of IFAC)
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This paper delineates an application of two classes of parity-check codes to the design for failure-tolerant counters. They are 1) a modified first-order Reed-Muller code and 2) the perfect Hamming code. The first code employs a majority element for implementing the error-correcting scheme while the second one makes use of a variable 2j-2+1-out-of-2j-1+1 majority element. These coding techniques can be applied in principle to other logic hardware to increase its reliability.