Algebraic structure theory of sequential machines (Prentice-Hall international series in applied mathematics)
Failure-Tolerant Sequential Machines with Past Information
IEEE Transactions on Computers
IEEE Transactions on Computers
Fault Tolerant Sequential Machines
IEEE Transactions on Computers
Realization of Fail-Safe Sequential Machines by Using a k-out-of-n Code
IEEE Transactions on Computers
N-Fail-Safe Sequential Machines
IEEE Transactions on Computers
Coding Techniques for Failure- Tolerant Counters
IEEE Transactions on Computers
Redundancy by Coding Versus Redundancy by Replication for Failure-Tolerant Sequential Circuits
IEEE Transactions on Computers
Fault-Tolerant Computers Using ``Dotted Logic'' Redundancy Techniques
IEEE Transactions on Computers
Hi-index | 14.98 |
Given a synchronous sequential machine M, this correspondence deals with the fault-tolerant realization M of M and also its fail-safe realization M on the assumption that the faults that can occur to the circuitry of M or M are of permanent stuck-at type and the total number of faults can be at most some preset positive integer r. First, the realization of M or M is derived for r = 1 and then the same idea is extended to have the realization for any arbitrary r. It has been shown that the realization of M is such that it is also able to tolerate faults of nonpermanent nature.