Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Algebraic structure theory of sequential machines (Prentice-Hall international series in applied mathematics)
Failure-Tolerant Sequential Machines with Past Information
IEEE Transactions on Computers
Fault Tolerant Sequential Machines
IEEE Transactions on Computers
Coding Techniques for Failure- Tolerant Counters
IEEE Transactions on Computers
Redundancy by Coding Versus Redundancy by Replication for Failure-Tolerant Sequential Circuits
IEEE Transactions on Computers
Fault-Tolerant Computers Using ``Dotted Logic'' Redundancy Techniques
IEEE Transactions on Computers
| Hi-index | 14.98 |
This correspondence deals with the fault-tolerant realization of a sequential machine using error-correcting (n,k) linear codes. Earlier works in the same area confine their attention to modified Reed-Muller Code and perfect Hamming Code and achieve the realization using a number of majority logic gates, which makes the entire realization quite complex. The realization discussed in this paper needs a smaller number of circuit components with less complexity.