Concurrent Fault Detection in Microprogrammed Control Units
IEEE Transactions on Computers
State assignment using a new embedding method based on an intersecting cube theory
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
State assignment for hardwired VLSI control units
ACM Computing Surveys (CSUR)
Optimized state assignment of single fault tolerant FSMs based on SEC codes
DAC '93 Proceedings of the 30th international Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Self-checking sequential circuits with self-healing ability
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Simplifying Sequential Circuit Test Generation
IEEE Design & Test
Concurrent Error Detection Using Monitoring Machines
IEEE Design & Test
Synthesizing Fast, Online-Testable Control Units
IEEE Design & Test
Automatic Synthesis of Self-Recovering VLSI Systems
IEEE Transactions on Computers
Algebraic techniques for the optimization of control flow checking
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
14.1 Fast Self-Recovering Controllers
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Finite State Machine Synthesis with Concurrent Error Detection
ITC '99 Proceedings of the 1999 IEEE International Test Conference
On Concurrent Error Detection with Bounded Latency in FSMs
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A Formal Approach to On-Line Monitoring of Digital VLSI Circuits: Theory, Design and Implementation
Journal of Electronic Testing: Theory and Applications
Efficient Concurrent Self-Test with Partially Specified Patterns
Journal of Electronic Testing: Theory and Applications
Periodic and non-concurrent error detection and identification in one-hot encoded FSMs
Automatica (Journal of IFAC)
Circuit Level Concurrent Error Detection in FSMs
Journal of Electronic Testing: Theory and Applications
| Hi-index | 14.99 |
A method for introducing online test facilities in a controller with a very low overhead is presented. This online test consists of detecting illegal paths in the control flow graph. These illegal paths may be due either to permanent faults or to transient errors. The state code flow is compacted through polynomial division. An implicit justifying signature method is applied at the state code level and ensures identical signatures before each join mode of the control flow graph. The signatures are then independent of the path followed previously in the graph, and the comparison to reference data is greatly facilitated. This property is obtained by a state assignment, nearly without area overhead. The controllers can then be checked by signature analysis, either by a built-in monitor or by an external checker.