Optimized Synthesis of Concurrently Checked Controllers
IEEE Transactions on Computers
Self-checking and fault-tolerant digital design
Self-checking and fault-tolerant digital design
Concurrent Error Detection Using Monitoring Machines
IEEE Design & Test
Survivable Self-Checking Sequential Circuits
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Algebraic techniques for the optimization of control flow checking
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Self-Checking of FPGA-Based Control Units
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Self-Checking FSM Design with Observing only FSM Outputs
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
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In this paper we deal with totally self-checking (TSC) synchronous sequential circuits (SSCs), that are able to recover after an occurrence of a fault. We call SSC owing this property as a self-healing SSC. A concept of a partially monotonic SSC is used in the paper. It is shown that the partially monotonic SSCs satisfy the self-healing property. A novel reduced m-out-of-n code is developed. It is proposed applying this code to the synthesis of a TSC checker for the state monotonic SSCs. The proposed method of synthesis is based on a LUT implementation of monotonic functions.For most circuits in a standard benchmark set, the proposed approach leads to a reduction of about 10-20% of the overhead as compared with the traditional methods.