Error-control coding for computer systems
Error-control coding for computer systems
Optimized Synthesis of Concurrently Checked Controllers
IEEE Transactions on Computers
An efficient procedure for the synthesis of fast self-testable controller structures
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Fault-tolerant computer system design
Fault-tolerant computer system design
Concurrent Error Detection Using Monitoring Machines
IEEE Design & Test
Fast Controllers for Data Dominated Applications
EDTC '97 Proceedings of the 1997 European conference on Design and Test
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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A target structure for implementing fast online testable control units for data-dominated applications is presented. In many cases, the proposed controller structure leads to a performance improvement of more than 30% for a standard benchmark set whereas the area overhead is less than 15% compared with conventional on-line testable finite state machines (FSM). The proposed approach is compatible with the state-of-the-art methods for FSM decomposition, state encoding and logic synthesis.