Communications of the ACM - Special section on computer architecture
A reconfigurable and fault-tolerant VLSI multiprocessor array
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Distributed fault-tolerance for large multiprocessor systems
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
X-Tree: A tree structured multi-processor computer architecture
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
A multiprocessor network suitable for single-chip VLSI implementation
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Optimal Elections in Faulty Loop Networks and Applications
IEEE Transactions on Computers
All-to-All Personalized Communication Algorithms in Chordal Ring Networks
ICN '01 Proceedings of the First International Conference on Networking-Part 2
On reliability analysis of forward loop forward hop networks
ICDCIT'06 Proceedings of the Third international conference on Distributed Computing and Internet Technology
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Certain fault-tolerant multiprocessor networks that can emulate linear array interconnections are considered. The system is fault tolerant of (m-1) node and link failures. One of the particularly attractive features of this network is that it allows for a linear array structure starting with any node even in spite of (m-2) faults. The configuration algorithm is fully distributed, and is performed on the basis of test results obtained from nonfaulty processors only. A simple fault identification procedure is developed using the above routing algorithm.