IEEE Transactions on Computers
A Multiple Fault-Tolerant Processor Network Architecture for Pipeline Computing
IEEE Transactions on Computers
Tolerance of Double-Loop Computer Networks to Multinode Failures
IEEE Transactions on Computers
IEEE Transactions on Computers
Efficient construction of catastrophic patterns for VLSI reconfigurable arrays
Integration, the VLSI Journal
On enumeration of catastrophic fault patterns
Information Processing Letters
Fault-Tolerant Meshes and Hypercubes with Minimal Numbers of Spares
IEEE Transactions on Computers
On characterization of catastrophic faults in two-dimensional VLSI arrays
Integration, the VLSI Journal
Analysis of Chordal Ring Network
IEEE Transactions on Computers
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A common technique to improve the reliability of loop (or ring) networks is by introducing link redundancy; that is, by providing several alternative paths for communication between pairs of nodes. With alternative paths between nodes, the network can now sustain several node and link failures by bypassing the faulty components. However, faults occurring at strategic locations in a ring can prevent the computation by disrupting I/O operations, blocking the flow of information, or even segmenting the structure into pieces which can no longer be suitable for any practical purpose. An extensive characterization of fault-tolerance in FLFH networks is given in this paper. The characterization has revealed several properties which describe the problem of constructing subrings and linear arrays in the presence of node failures in the FLFH network for a specific link configuration. Also in this paper, bounds are established on the degree of fault tolerance achievable in a redundant FLFH network when performing a computation that requires a fixed number of operational nodes. Also the bounds on the size of the problems guaranteed to be solved in the presence of a given number of faults in the network are derived.