A Linear Algebraic Model of Algorithm-Based Fault Tolerance
IEEE Transactions on Computers
Embedding triple-modular redundancy into a hypercube architecture
C3P Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1
Fault-Tolerant Array Processors Using Single-Track Switches
IEEE Transactions on Computers
On the Design of Fault-Tolerant Two-Dimensional Systolic Arrays for Yield Enhancement
IEEE Transactions on Computers
IEEE Transactions on Computers
Bi-Level Reconfigurations of Fault Tolerant Arrays
IEEE Transactions on Computers
Meshes with flexible redundancy
Proceedings of the international workshop on Algorithms and parallel VLSI architectures II
An Efficient Modular Spare Allocation Scheme and Its Application to Fault Tolerant Binary Hypercubes
IEEE Transactions on Parallel and Distributed Systems
A reconfigurable and fault-tolerant VLSI multiprocessor array
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Information Processing Letters
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Different multiple redundancy schemes for fault detection and correction in computational arrays are proposed and analyzed. The basic idea is to embed a logical array of nodes onto a processor/switch array such that d processors, 1/spl les/d/spl les/4, are dedicated to the computation associated with each node. The input to a node is directed to the d processors constituting that node, and the output of the node is computed by taking a majority vote among the outputs of the d processors. The proposed processor/switch array (PSVA) is versatile in the sense that it may be configured as a nonredundant system or as a system which supports double, triple or quadruple redundancy. It also allows for spares to be distributed in the PSVA in a way that permits spare sharing among nodes, thus enhancing the overall system reliability. In addition to choosing the required degree of redundancy, the flexibility of the PSVA architecture allows for the embedding of redundant arrays onto defective PSVA's and for run-time reconfiguration to avoid faulty processors and switches. Different embedding and reconfiguration algorithms are presented and analyzed using Markov chain techniques, using probability arguments, and via simulation.