A reconfigurable and fault-tolerant VLSI multiprocessor array
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
IEEE Transactions on Computers
The Rule-Based Approach to Reconfiguration of 2-D Processor Arrays
IEEE Transactions on Computers
Computational Arrays with Flexible Redundancy
IEEE Transactions on Computers
Some Prospects for Efficient Fixed Parameter Algorithms
SOFSEM '98 Proceedings of the 25th Conference on Current Trends in Theory and Practice of Informatics: Theory and Practice of Informatics
Design of a highly reconfigurable interconnect for array processors
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
A dynamically reconfigurable interconnect for array processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The authors propose a unified approach to the design of the fault-tolerant systolic arrays incorporating design for testability, a testing scheme, a reconfiguration algorithm, time-complexity analysis of the proposed reconfiguration algorithm, and yield analysis. A main feature of the proposed designs is that multiple processing elements in a 2-D array can be tested simultaneously, thus reducing the testing time significantly. Another feature is that with the introduction of delay registers, the proposed reconfiguration algorithm reconfigures a faulty 2-D systolic array into a fault-free array without reducing throughput. The overall aim is to provide a design for a 2-D systolic array that produces high yield in VLSI/WSI implementations