On the Design of Fault-Tolerant Two-Dimensional Systolic Arrays for Yield Enhancement
IEEE Transactions on Computers
IEEE Transactions on Computers
On the reconfiguration of vlsi/wsi processor arrays
On the reconfiguration of vlsi/wsi processor arrays
IEEE Transactions on Computers
Submesh Determination in Faulty Tori and Meshes
IEEE Transactions on Parallel and Distributed Systems
On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast and efficient submesh determination in faulty tori
HiPC'04 Proceedings of the 11th international conference on High Performance Computing
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The authors propose to set up assignment rules based on the available interconnection resources of 2-D processor arrays. The reconfiguration of 2-D processor arrays is guided by the assignment rules, such that logical cells are always connected through the available interconnection resources. The advantage of the proposed approach is the easy adaptation to various system requirements, by adjusting assignment rules. The proposed reconfiguration algorithm can be extended to arrays with clustered faulty cells, overcoming the weakness of fixed domain approaches.