Fault-tolerant wafer-scale architectures for VLSI
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
A reconfigurable and fault-tolerant VLSI multiprocessor array
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
A Study of Two Approaches for Reconfiguring Fault-Tolerant Systolic Arrays
IEEE Transactions on Computers
| Hi-index | 14.98 |
The problem of restructuring systolic arrays with faulty cells is considered. An approach to derive the required data-flow paths and computational sites is proposed. The data skewing requirement, which must be satisfied to find an input schedule, is also discussed. Algorithms to restructure systolic arrays for three different architectures of processing elements are presented. A systematic method to retime the restructured array using additional programmable delays so that the retimed array satisfies the data skewing requirements is developed.